Mobility enhancement of nanoscale biaxial strained silicon metal-oxide semiconductor field effect transistor

Abstract

Scaling down of Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices has been a driving force in IC industry due to high speed and low power requirements. The recent MOSFET devices have been scaled down to 50nm gate lengths where the gate oxide thickness has become thin enough to suppress the short channel effect (SCE). However further scaling down of the MOSFET beyond 50nm will cause the SCE, degrading the current drivability and electron mobility of a MOSFET. Therefore further improvement without minimizing the gate length is strongly required. Strained silicon (Si) is a promising candidate for improving the performance of MOSFET technology without compromising the control of short channel effects since it provides device performance enhancements through changes in material properties rather than changes in device geometry or doping. In this research, the design, fabrication and characterization of high speed and low power performance for 100nm of strain silicon P-type Metal Oxide Semiconductor (PMOS) structures are experimented. With an oxide thickness of 5nm and germanium (Ge) concentration of 30%, the threshold voltage for the strained Si and unstrained structures are -0.74V and -0.96V, respectively. In addition, strained Si shows approximately 20% enhancement in drain current compared to the unstrained structure. The increase of valence band in strained Si as compared to unstrained Si indicates the split of the energy band. This causes holes to increasingly occupy the top band and would increase the mobility of strained Si . The strained Si shows mobility enhancement compared to unstrained structure. Meanwhile, the effect of Ge concentration to strained Si showed that as Ge concentration increased from 20% to 40%, the drain current and hole concentration is increased while the threshold voltage decreased. However moderate Ge concentration must be chosen with suitable strained Si thickness in order to prevent lattice mismatch. The results show that the strained Si critical thickness is 10nm with a 30% Ge concentration for the single channel strained Si. The strained Si exhibits low threshold voltage as the strained Si thickness increases from 5nm to 8nm. Therefore 7nm strained Si thickness was used to create strained Si with 30% Ge concentration. Simulations provide more realistic results and allow researchers to gain a better understanding of the effects of different device parameters on the overall device performance without fabrication.