Network-on-chip network adapter

Abstract

Network-on-Chip (NoC) is a new paradigm for System-on-Chip (SoC) onchip communication to replace existing bus-based system which is inadequate to cater the growing complexity of SoC. This on-chip design involves a huge number of components that need to communicate with each other to carry their functions, which could affect the design effort, scalability and testability of the SoC in general. This report presents the design and implementation of NoC network adapter which by using Wishbone interface to interconnect IP cores to the network. This network adapter architecture provides four types of best-effort (BE) services to IP core with blocking-type operation. NA segmentizes, packetizes the outgoing data into flits, and sends to router. NA also reassembles and decodes the incoming flits into original data before present them to destination core. NA is designed in Verilog hardware language using Altera Quartus II development software. Functional simulations and performance for each BE types are analyzed to ensure the design can function and meet the objectives and specifications of the project. This architecture uses 575 logic elements and could operate up to 139.74 MHz. This NA dissipates power approximately 90 mW for read operation and 98mW for write operation. NA BE latency depends on type of operations, which vary from 16.5 to 22.5 clock cycles.