Universiti Teknologi Malaysia Institutional Repository

VHDL implementation of pipelined DLX microprocessor

Anthony, Ignatius Edmond (2008) VHDL implementation of pipelined DLX microprocessor. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.

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Abstract

The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good architectural model for study, not only because of the popularity of this type of machine, but also because it is easy to understand. Utilizing open source hardware such as the DLX core yields the apparent advantage of free-for-all distribution as well as having source codes that are is available and open, allowing for source code modification at-will. This project aims to continue previous work on integration of the DLX core by adding instruction pipelining which was excluded from the previous project’s scope due to complexity and time limitations. Instruction execution speedup and performance was left on the table to be dealt with in future work. Since the DLX microprocessor was, by nature, a 5-stage pipelined microprocessor, it can be expected that the core’s performance on instruction execution can be sped up with a pipeline implementation. Comparison between the non-pipelined and pipelined DLX were also performed to verify this instruction execution speedup expectation.

Item Type:Thesis (Masters)
Additional Information:Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroeletronik)) - Universiti Teknologi Malaysia, 2008; Supervisor : Prof. Muhammad Mun'im bin Ahmad Zabidi
Uncontrolled Keywords:VHDL (Computer hardware description language), microprocessors, pipeline
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Computer Science and Information System (Formerly known)
ID Code:11462
Deposited By: Ms Zalinda Shuratman
Deposited On:16 Dec 2010 06:21
Last Modified:10 Sep 2012 02:55

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