Mathematical modelling and optimization of multisite efficiency to reduce cost of test in semiconductor final test process using Taguchi method

Abstract

This study proposes improved equations for semiconductor multisite testing process. It contributes to the derivation of the new equations which have better prediction accuracy of multisite efficiency (MSE), testing throughput, and cost of test than the conventional ones to enable accurate conduct of test equipment optimization. This process is achieved by developing new equations which consider ten MSE variables identified in the previous literature and equipment technical specifications where three equations, namely, the MSE equation, testing throughput equation, and cost of test equation, are developed. The developed equations are validated through a Mean Absolute Percentage Error (MAPE). The testing throughput equation is validated to be accurate with 2.58% MAPE compared with 24.02% MAPE for the conventional testing throughput equation. This finding shows that the equations need to include all the related variables for accurate prediction. The study conducts optimized parameter setting for MSE and testing throughput using the Taguchi robust parameter design (L9 orthogonal array), and then analyzes confirmation test for MSE and testing throughput. The MSE and testing throughput are verified to be reproducible with a percentage gain difference of 5.38 (optimum versus worst) and 1.94 (optimum versus current) for MSE and 1.54 (optimum versus worst) and 4.67 (optimum versus current) for testing throughput, which is below 30% of the gage repeatability and reproducibility acceptable level. This finding proves that the control factors significantly affect the MSE and testing throughput. The ideal function graph for MSE and testing throughput shows that the increment of test site significantly affects the MSE and testing throughput, where the higher test site configuration eliminates the effect of the noise factors compared with the lower test site configuration. A cost of test analysis is performed with the Taguchi Loss Function (TLF) to determine which multisite setting produces the cheapest cost of the test relative to MSE. The finding shows that the increment of test site reduces the MSE percentage to achieve the break-even point. If all test site configurations have the same MSE level, then, the X32-site produces the cheapest cost of test. If the MSE of the X32 site drops by 5% compared with the X16 site, then, the X16 site produces a cheaper cost of test. Similarly, if the MSE of X16 sites drops by 5% compared with the octal site, then, the octal site produces a cheaper cost of test. The configuration of X32 sites needs to maintain at least 91% MSE to produce a cheaper cost of the test compared with octal sites. This finding concludes that if the increment of test site cannot sustain the MSE, then, the cost of the test increases. The novelty of this research is the guideline development for cost-effective multisite configuration which is very critical in the semiconductor industry, and it has never been mentioned in any study before. It is a major contribution to the semiconductor test industry, particularly for selecting a cost-effective multisite configuration so that firms can manage their profit and loss accurately rather than simply increasing the test site without understanding its effect on the cost of the test.