Device simulation of the electrical characteristics in 14nm gaussian channel junctionless finfet

Abstract

In conventional FinFET, it becomes difficult to define the doping concentration of material over a distance shorter than 10nm and produce high-quality junctions for sub 20nm regime which leads to short channel effects. Hence, Junctionless FinFET which offers architecture, free from any p-n junction is able to overcome the short channel effects. JL FinFET acts like a gated resistor and it has uniform high doping (~ 1019 to 1020 cm-3) from source to drain throughout the silicon channel to maintain a high drive current in ON state. The prominent advantages of this device include low leakage current, low parasitic capacitance, reduced Drain Induced Barrier Lowering (DIBL), and excellent Ion/ Io f f ratio which made them a viable option for low-power logic applications. Apart from their advantages, the most important issue for the fabrication of Junctionless devices is achieving a uniform doping concentration in the device layer, especially in non-planar structures like FinFET. In FinFET, doping of the fin region has to be performed in a 3D fashion which results in non-uniform doping around the fin. Hence the most general doping profile is the Gaussian which is considered as a solution for this doping concern. This work presents the design and optimization of the 14nm Gaussian Channel Junctionless FinFET (GC-JLFinFETs) using Silvaco TCAD simulator. In this study, the results are validated using the conventional FinFET and the structure is optimized to improve the ON current (Ion) with a simultaneous decrease in the OFF current (Io ff), Subthreshold Swing (SS), and Drain-Induced Barrier Lowering (DIBL). Hence the structure is optimized with respect to the device parameters such as high-k spacer dielectric, low-k gate dielectric, and spacer width. The Gaussian doping profile in JL-FinFET structure is analyzed with the peak of 4 x 1019 cm-3 placed at the sidewalls of Fin and gets reduced gradually towards the center of the Fin with the standard deviation of 1nm/dec. The gate work function of all the configurations of FinFET was adjusted to obtain a 400mV threshold voltage for a meaningful comparison. In order to further reduce the leakage current of the device, Punch Through Stop Layer (PTS layer) has been added beneath the channel. The IV characteristics are simulated for both n- and p-type FinFET exhibits good compliance with the experimental results of Intel. For a fair device simulation, the device is carefully calibrated using the experimental results thus validating the simulation results. The simulated values interpret that the Ion=101.5^A/ |im is obtained for the simulated device structure. The simulated design shows better efficiency in terms of short channel characteristics namely DIBL= 25.3 mV/V, SS = 63.88 mV/dec, Transconductance =3.621x105 S/^m, and the overall efficiency of the device is improved by 25.63%. The work is further extended to its application in inverter circuits using the SPICE simulator to analyze the circuit level performance of the simulated structure. In SPICE level, the circuit is subjected to DC and transient analysis for its feasibility in real-time application of the device, and the obtained improvement is 42.58%.