Multi-core 16-bit CPUs for PLC processor

Abstract

PLCs (Programmable Logic Controllers) are in great demand across a wide range of industries. A PLC can be used to model a controlled processing plant using a Ladder Logic Diagram (LLD). The PLC will read all the sensors, process the logic network of input and output, and provides the corresponding output signals to all actuators. LLD is widely being used to model most of the PLCs on the market today since it is user-friendly and simple to grasp by users from different levels of background. The PLC in this research will be sped up by employing a Ladder Rung Processor (LRP) architecture in a Field Programmable Gate Array (FPGA). However, LRP is only good for binary inputs. For more than a single bit input or data processing, a general purpose CPU is needed to save resources. The trend toward concurrent processing, resulting in multicore CPUs, will make it easier for a PLC processor to complete numerous tasks at the same time, enhancing performance under the demands of powerful applications and programmes. As an example of controlling a 5 axes robotic arm, a single core CPU of PLC can only control a maximum of 2 axes at the same time. Hence, a combination of LRP and multicore CPU approach can increase the throughput of a PLC processor to do concurrent processing for automation, control and robotic applications. Several architectures of multicore CPU will be investigated before determining the best solution for a PLC processor. Therefore, several performances of multicore CPU for a PLC processor will be evaluated. A RISC based CPU will be used in this research due to its simplicity while maintaining the possibility for future expansion. A 16 bits RISC CPU will be the baseline reference in this research. Several modifications will be done in terms of memory allocation and task scheduling for each of the cores will be tackled to make sure they are fully utilized in order to boost the performance to maximum. Verilog HDL language will be the preference language in the designation of multicore PLC processor. The cyclic scans frequency of PLC will be the performance benchmark that will be compared with the existing PLC in the market. To verify the architecture of multicore PLC processor, simulation on a PC and interfaced with a PLC on an FPGA will be implemented. A multicore approach in designing a complete PLC processor will increase the overall performance compared to a single core PLC processor by handling multiple processes in a manufacturing line.