An efficient March (5n) FSM-Based Memory Built-In Self Test (MBIST) architecture

Abstract

Embedded memory is the most common circuitry in all System on Chip (SoC). It is also a critical circuit that is difficult to be tested effectively and efficiently by using external testing equipment, therefore the testing cost is expensive. Memory Built-in Self Test (MBIST) which is a self-test circuit added to the memory under test is the solution for effective and efficient embedded memory testing. Area overhead and test time are the concern in the memory testing with MBIST. There are many MBIST architectures available such as microcode-based, FSM-Based and Counter-based. Each of the architectures has its own pros and cons. The microcode-based MBIST requires a longer test time and consumes a large area. Above all, FSM-Based MBIST has better area overhead as compare with Microcode-based but it is less flexible. Counter-based MBIST has low area overhead with trade off of less flexibility. The MBIST is exercising based on the testing algorithms such as March algorithms. However, existing March algorithms are of the minimal length on the respective fault. In this paper, a new March-based testing algorithm is proposed, called March (5n) which is using the address for generating data pattern provide an alternative form of March based algorithm and it is implemented with an FSM-Based MBIST that consists of a March (5n) controller, an address generator, a data generator, and a memory interface. It is found that the proposed March (5n) testing algorithm can provide higher fault coverage than conventional MATS+ and test time 1.2 times faster than conventional MATS++ testing algorithms.