A new asymmetrical multilevel inverter topology with reduced device counts

Abstract

In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be done by arranging available switches and dc sources in a fashion such that the maximum combination of addition and subtraction of the input dc sources can be achieved. Comparison between the existing topologies shows that the proposed topology yields less component counts. To verify the viability of the proposed topology, the circuit model is developed and simulated in Matlab-Simulink software. A low frequency switching strategy is also proposed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage with less number of component counts and acceptable harmonic distortion content.