Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET

Abstract

The digital multipliers are the assertive sources of power exhaustion in the modern digital systems. To perform most efficient arithmetic based calculations, Montgomery multiplication can be one of the best alternatives for other conventional methods in digital architecture as high-speed multipliers are desired for its remarkable performance. The main drawback of the digital multipliers is that power exhaustion is very high when compared to the other elements of the digital circuit. Shift register is the one of the most important component in a digital multiplier which consumes comparatively higher power than the other components. Shift registers contains a series of D-flip flops to store the digital data. In order to obtain a notable improvement in terms of power consumption at the chip level, the flip-flop can be modified to achieve the reduction of average power in the multiplier. The Fin-Field Effect Transistor (FinFET) is a promising candidate to overcome fundamental limitations of its Silicon based alternative MOSFET. However, there seems to be an increase in leakage power and delay. The Junctionless FinFET with uniform doping in the channel proves to offer a better performance in terms of overall speed, power consumption and power delay product. The architecture has been designed in 7nm FinFET and JL-FinFET in Synopsys HSpice and Silvaco TCAD. The results of the Montgomery Multiplier affirms that the overall energy is improved by 55% and speed of the device by 35% as compared to the existing Montgomery Multiplier.