A novel single-phase pwm asymmetrical multilevel inverter with number of semiconductor switches reduction

Abstract

In this paper, a new asymmetrical multilevel inverter topology (MLI) is proposed with the objectives of using decreased number of semiconductor switches, dc voltage sources, gate driver circuits and dc links. The structure of presented MLI is very simple and modular. The fundamental module of this structure consists of nine semiconductor switches (eight unidirectional and one bidirectional) and four asymmetrical configured DC sources (ratio of 1:2), which can generate 13-level output voltage. To validate the design, a Matlab-Simulink based model is developed. For this paper, a Sinusoidal Pulse Width Modulation (SPWM) is deployed as the switching strategy of the proposed MLI. The circuit model is simulated under pure resistive and inductive loads. It will be shown that the circuit performs well under both loads. Comparison with traditional MLIs and other recently introduced MLIs will be conducted to show the superiority of the proposed MLI in terms of reduced number of devices and lower voltage stress across the switches.