Universiti Teknologi Malaysia Institutional Repository

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model

Ayat, Sayed Omid and Hani, M. Khalil and Ab. Rahman, Ab. Al-Hadi (2018) Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model. Turkish Journal of Electrical Engineering and Computer Sciences, 26 (2). pp. 919-935. ISSN 1300-0632

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Official URL: http://dx.doi.org/10.3906/ELK-1706-222


In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its exibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Rooine model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

Item Type:Article
Uncontrolled Keywords:energy efficiency, Roo ine model
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:85533
Deposited By: Widya Wahid
Deposited On:30 Jun 2020 16:50
Last Modified:30 Jun 2020 16:50

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