Evaluation of scheme selection and parameter effects in the reconfigurable transmitting power in Wireless Network-on-Chip

Abstract

Wireless Network-on-Chip (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. Current WiNoC architectures employ constant maximum transmitting power for communicating radio hubs regardless of physical location of the receiver. Recently, two closed loop reconfigurable power schemes that dynamically calibrate the transmitting power level needed for communication between the hubs based on bit error rate (BER) have been proposed. In this paper, these schemes are compared in terms of latency, power and area overheads. Both schemes achieve significant energy savings with limited performance degradation and insignificant impact on throughput. Only a small fraction of both area and power overheads are introduced (about 0.1%). The schemes are general and can be applied on any WiNoC architecture.