Universiti Teknologi Malaysia Institutional Repository

Runtime network-on-chip thermal and power balancing

Rusli, M. S. and Marsono, M. N. and Husin, N. S. (2017) Runtime network-on-chip thermal and power balancing. Applications of Modelling and Simulation, 1 (1). pp. 36-41. ISSN 2600-8084

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Abstract

In Network-on-Chip (NoC), most thermal and peak power balancing methods are monitored by centralized power/thermal managers. This increases inter-core communication latency and imbalanced thermal distribution. These factors directly affect the hot spot formation caused by high power densities developed with increasing per-core transistor number. As a result, reliability decreases along with static power dissipation. This proposal aims to introduce hierarchical agents for balancing power and thermal distribution by manipulating system’s parameters such as power, thermal, voltage below the optimal values. As some level of control is applied, this proposal also targets to achieve network scalability by implementing some level of independencies; self-organize and self-optimize distributed agent in overcoming core-level homogeneous processing element (PE) thermal and power variations at runtime. The aims of this work are to significantly contribute to achieving runtime thermal and power balancing, power and thermal management and reducing thermal hot spot formation in NoC.

Item Type:Article
Uncontrolled Keywords:Network-on-Chip (NoC), thermal balancing, power and thermal management, homogeneous MPSoC, runtime
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:80736
Deposited By: Fazli Masari
Deposited On:27 Jun 2019 06:20
Last Modified:27 Jun 2019 06:20

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