Low noise and low power ECG amplifier using cmos 0.13μm technology

Abstract

Through the scaling down of modern VLSI technologies, the realization of CMOS based electrocardiogram (ECG) device becoming wearable to its user is possible. Yet, this transition introduces more constraints to its analog circuits. This is due to the measured electrical signal of ECG devices, or known as ECG signal possessed characteristics that are low in frequency (0.1 to 150Hz) and amplitude (<5mV), thus it lead to every ECG devices suffered from flicker noise for low frequency cardiac signal acquisition at the front-end of its sensor, 50 Hz power line electromagnetic interference, and the large unstable input offsets due to the improper attachment of electrode-skin interface. Therefore, to encounter this problem, the frontend of ECG devices, which is amplifier needed to be enhance so it able to accurately detect the ECG signals. Besides that, the amplifier must able to operate at low voltage and less power consumption so that it can be used in wearable device. In this work, a high performance CMOS amplifier for ECG sensors that improves the noise issue and suitable for low power wearable cardiac screening is designed. The designed circuit adopts the folded cascode topology to achieve high gain and less susceptible to noise. This work uses 0.13 μm CMOS process technology from Silterra and Mentor Graphics Pyxis as the design tool. This successfully achieve high CMRR which is 160dB. Besides that, this work also able to reduce the noise at the front-end amplifier system down to 1.28nV/√Hz. The power consumption of the designed amplifier is 3 μW, which is low and suitable to be implemented on design for wearable ECG devices.