Monemi, A. and Ooi, C. Y. and Palesi, M. and Marsono, M. N. (2017) Ping-lock round robin arbiter. Microelectronics Journal, 63 . pp. 81-93. ISSN 0026-2692
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Abstract
Arbiter is the core element in shared-resources systems such as in network-on-chip (NoC), conventional interconnection buses and computer network switch schedulers. Arbiters are located in the critical path delay (CPD) of these systems, that necessitates fast and fair arbitration. This paper proposes two gate-level arbiter architectures. The first arbiter is an improved ping-pong arbiter (IPPA) that is optimized to offer lower execution delay compared to existing round robin arbiters (RRAs). One of the main disadvantages of ping-pong arbiter (PPA) is that fair arbitration is limited to the uniformly-distributed active requests pattern. To solve this problem, we propose a new gate-level RRA, called ping-lock arbiter (PLA). PLA, which is an improved IPPA offers fair arbitration under any distribution of active requests and has the advantage of low execution delay. The FPGA and ASIC implementations of PLA show up to 18% and 12% improvement in average delay, respectively, when compared to existing RRAs in literature.
Item Type: | Article |
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Uncontrolled Keywords: | Fair arbitration, Round robin arbiter |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
Divisions: | Electrical Engineering |
ID Code: | 76961 |
Deposited By: | Fazli Masari |
Deposited On: | 30 Apr 2018 14:30 |
Last Modified: | 30 Apr 2018 14:30 |
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