Test register insertion at RTL based on reduced BIST

Abstract

Built-in self-test (BIST) method has high area overhead and long test application time. In this paper, a new BIST method is proposed at register transfer level (RTL) as a design for testability (DFT) method to modify a given RTL circuit to a reduced BISTable RTL circuit. First, we introduce modelling method called extended R-graph to represent the register connectivity of an RTL circuit. The original register in the RTL circuit is modified into multiple input signature registers (MISRs) as test register. The selection of MISR is performed by extended minimum feedback vertex set (MFVS) algorithm that identifies a set of vertices (representing test register) which breaks all the loops of extended R-graph with minimal cost when vertices are removed. It has been proven through simulation that the proposed BIST method has lower area overhead of 32.9% on average and achieves comparably high fault coverage compared to the previous method, concurrent BIST using ITC'99 benchmark circuits.