An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Abstract

Shrinking technologies to deep sub-microns has raised demands for high quality testing. However, excessive power during test application time serves as limiting factors for reliability in testing. To address these issues, we have proposed Integrated Low Power Gating (ILPG) Scan Cell to alleviate shift power consumption by modifying conventional master-slave scan cell. It is able to reduce power consumption inside the scan cell as well as to gate the redundant transitions propagation from scan chain to combinational part during shifting. Another low power gating scan cell for critical paths, called Critical Path Integrated Low Power Gating (CPILPG) Scan Cell, has been proposed. It speeds up the data launch operation in normal/capture mode compared to ILPG scan cell through the utilization of transmission gate. Both designs use a shorter shift path to improve critical path delay and reduce power in scan chain. This allows shift frequency increase further within maximum power budget. Hence, test application time is shortened. Our post-layout experiment results show an average power reduction of 15.12% for ILPG over conventional scan cell and up to 39.15% improvement compared to one of the most popular gating techniques. In addition, 51.42% and 43.94% improvements in CLK-to-shift delay over conventional scan cell are achieved for ILPG and CPILPG, respectively.