Yion, K. Z. and Rahman, A. A. H. A. (2017) Exploring the design space of HEVC inverse transforms with dataflow programming. Indonesian Journal of Electrical Engineering and Computer Science, 6 (1). pp. 104-109. ISSN 2502-4752
|
PDF
445kB |
Official URL: https://www.scopus.com/inward/record.uri?eid=2-s2....
Abstract
This paper presents the design space exploration of the hardware-based inverse fixed-point integer transform for High Efficiency Video Coding (HEVC). The designs are specified at high-level using CAL dataflow language and automatically synthesized to HDL for FPGA implementation. Several parallel design alternatives are proposed with trade-off between performance and resource. The HEVC transform consists of several independent components from 4x4 to 32x32 discrete cosine transform and 4x4 discrete sine transform.This work explores the strategies to efficiently compute the transforms by applying data parallelism on the different components. Results show that an intermediate version of parallelism, whereby the 4x4 and 8x8 are merged together, and the 16x16 and 32x32 merged together gives the best trade-off between performance and resource. The results presented in this work also give an insight on how the HEVC transform can be designed efficiently in parallel for hardware implementation.
Item Type: | Article |
---|---|
Uncontrolled Keywords: | FPGA, IDCT, Transform, Video Coding |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
Divisions: | Electrical Engineering |
ID Code: | 74905 |
Deposited By: | Widya Wahid |
Deposited On: | 22 Mar 2018 10:57 |
Last Modified: | 22 Mar 2018 10:57 |
Repository Staff Only: item control page