Universiti Teknologi Malaysia Institutional Repository

Hardware acceleration of a face detection system on FPGA

Dharan, S. V. and Khalil-Hani, M. K. M. and Shaikh-Husin, N. S. (2016) Hardware acceleration of a face detection system on FPGA. In: IEEE Student Conference on Research and Development, SCOReD 2015, 13 - 14 Dec 2015, Kuala Lumpur, Malaysia.

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Abstract

Face detection is a computer technology that has been used in various applications such as biometric authentication, surveillance, computer interaction and social media. It is the process of detecting faces in an image or video stream and is an important step that precedes face recognition. Many researchers in recent years are implementing real time and accurate face detection system on FPGA due to computing resource and design flexibility. This paper presents an implementation of a face detection system accelerated on FPGA for high throughput. The proposed system utilizes stream-oriented hardware architecture to perform image pre-processing, skin segmentation, filtering as well as connected component labeling processes. Window-based image processing such as median and morphological filtering were accelerated using line buffering technique to achieve maximum throughput. The detection system was implemented on an Altera Cyclone IV FPGA and was benchmarked against a software implementation using NIOS II soft-core processor. The hardware design achieved a speed-up of 250 times compared to software implementation when processing a RGB video frame of 800×600 pixel size.

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:face detection, FPGA, hardware acceleration, skin color segmentation
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:73318
Deposited By: Mohd Zulaihi Zainudin
Deposited On:20 Nov 2017 08:42
Last Modified:20 Nov 2017 08:42

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