Thermal model with metal consideration for System-On-Chip testing

Abstract

Increasing switching activities leads to high temperature during testing, which has adverse impact on circuit performance and reliability. Therefore, simulating thermal effects on System-on-Chip (SoC) when performing test scheduling is essential. However, most of the previous works on temperatureaware test scheduling were using thermal simulator that considers heat flow on silicon substrate only. Neglecting thermal effects caused by heat flow in metal interconnects may cause inaccuracy up to 30% as metal interconnect could remove a non-negligible amount of heat from the chip. This paper proposes an SoC thermal model that characterizes thermal effects due to metal interconnects under steady-state and transient stress conditions. The proposed thermal model is mainly based on RC network thermal model that is composed by thermal resistance and thermal capacitance of silicon substrate, heat spreader, heat sink as well as metal interconnects. Experiment has shown that our thermal model that does not consider metal interconnect effect is more accurate since it cause smaller temperature difference with the benchmark thermal simulation using ANSYS under assumption of 50% chip area being covered by a single layer of metal interconnect. The average temperature difference is just 1.904 °C compared to the temperature difference between the thermal model that considers metal effect and ANSYS thermal simulation.