Performance evaluation of silicon nanowire gate-all-around field-effect transistors and their dependence of channel length and diameter

Abstract

The performance of a semiconducting Silicon Nanowire (SiNW) Gate-All-Around (GAA) transistors as basic logic gates are assessed and tabulated for certain metric, against those of metal-oxide-semiconductor fieldeffect transistors (MOSFETs). Both SiNW and nano-MOSFET models agree considerably well with the trends available in experimental data. The simulation results show that silicon nanowire can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of SiNWFET and MOSEFET, namely propagation delay, energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. In addition, the influence of nanowire channel length and diameter over drain-induced barrier lowering (DIBL) and substhreshold swing (SS) in SiNWFET are also explored and compared with other experimental data. It has been shown that the SiNWFET model has a lower power-delay product (PDP) and energy-delay product (EDP) than of the 32 nm MOSFET Predictive Technology Model (PTM) in the circuit simulations. Shorter length and smaller diameter nanowire are desired to suppress short channel effects. Ultimately, SiNWFET have superior performance compared to nano-MOSFET due to the nearly ideal carrier transport in quasi-one dimensional structure.