Universiti Teknologi Malaysia Institutional Repository

Low latency Network-on-Chip router microarchitecture using request masking technique

Monemi, Alireza and Chia, Yee Ooi and Marsono, Muhammad Nadzir (2015) Low latency Network-on-Chip router microarchitecture using request masking technique. Intertiol Jourl Of Reconfigurable Computing, 2015 . ISSN 1687-7195

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Official URL: http://dx.doi.org/10.1155/2015/570836


Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

Item Type:Article
Subjects:A General Works
ID Code:58488
Deposited By: Haliza Zainal
Deposited On:04 Dec 2016 12:07
Last Modified:18 Sep 2017 10:43

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