Universiti Teknologi Malaysia Institutional Repository

A novel scan architecture for low power scan-based testing

Mojtabavi Naeini, Mahshid and Chia, Yee Ooi (2015) A novel scan architecture for low power scan-based testing. VLSI Design, 2015 (264071). ISSN 1065-514X

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Official URL: http://dx.doi.org/10.1155/2015/264071

Abstract

Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.

Item Type:Article
Uncontrolled Keywords:scan architecture, scan flip-flops
Subjects:N Fine Arts > NA Architecture
Divisions:Malaysia-Japan International Institute of Technology
ID Code:55787
Deposited By: Practical Student
Deposited On:06 Oct 2016 12:02
Last Modified:25 Aug 2017 09:36

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