Quasi-one-dimensional performance and benchmarking of CMOS-based multichannel carbon nanotube versus nanowire field-effect transistor models

Abstract

Performance assessment of carbon-based devices with carbon nanotube (CNT) as a protoype, and traditional silicon (Si) devices based on a nanowire is reported. Both CNT and nanowire (NW) present one-dimensional (1D) nanostructures making comparison relevant, connected, and future development of emerging technologies. The performance of a CNT as a rolled up graphene sheet is evaluated vis a vis that of the cylindrical Si NW. Compact models of Carbon Nanotube Field-Effect Transistors (CNTFET) and Silicon Nanowire Field- Effect Transistors (Si NWFET) that are developed, analysed, and conclusions drawn based on the 32-nm process technology. The CNTFET parameter is based on Stanford University model and Si NWFET model based on the BSIM-CMG 106.1.0 model form an excellent comparison and further expansion for industrial applications as new devices, circuits, and system-on-a-chip (SoC) are being evaluated for implementation. CNTFET offer a better compromise over and above the advantage of a Si NWFET extending More than Moore vision for industrial development. In fabrication processes, large contact sizes are usually used to connect the semiconducting channel tubes with metal probes. Therefore, by using an array of parallel tubes, the aspect ratio of unutilized channel to contact width can be increased significantly. In addition, each utilized channel contribute to larger output drain currents. Process engineer can use the authors' simple equation to calculate the sizes of the pitch, contact and spacer based on various technology process. It is important to note that both of the 32 nm CNTFET and Si NWFET show a reduction in the current when the number of tubes is greater than 12. The performance evaluation of these devices includes the comparison of drain induced barrier lowering (DIBL), subthreshold swing (SS) and on-off current for 1, 2, 5 and 10 tubes. Moreover, the energy-delay product (EDP) and power-delay product (PDP) are calculated to depict the tradeoff between the frequency of a propagating signal and power consumption limiting the packaging of devices on a chip. Last but not least, our finding shows that the digital performance of a multi-channel CNTFET at least one order of magnitude over the Si NWFET, both for EDP and PDP for 32 nm process.