Field programmable gate array architecture of proportional-integral-derivative controller

Abstract

Proportional-integral-derivative (PID) control is widely used in control and automation. PID implementation in software especially using microcontroller requires a lot of CPU execution time. The performance of PID controller can be improved by accelerating control function in hardware. Thus, the performance and throughput can be further improved when incorporated in FPGA architecture system. This project focuses on exploration of hardware architecture of PID controller and targeted for implementation on FPGA system. The architecture exploration include concurrent, serial and pipeline designs, functionality correctness and non-functional verification. These architectures was designed to support modularity and can be use for other control applications. Serial design architecture of PID is able to reduce - 60% of datapath unit resources compared to concurrent design but it required five cycles to produce the output. High throughput can be achieve using pipeline design and required 7 more registers compared to concurrent design with pipeline speed up about 1.5 and five times compared to serial design architecture.