Sarafi, Sahar and Hadidi, Kheyrollah and Abbaspour, Ebrahim and Aain, Abu Khari and Abbaszadeh, Javad (2014) 100 MS/s, 10-bit ADC using pipelined successive approximation. Journal of Circuits, Systems and Computers, 23 (5). ISSN 0218-1266
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Official URL: http://dx.doi.org/10.1142/S0218126614500571
Abstract
This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | analog-to-digital converter (ADC), pipelined successive approximation register (SAR) |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 51428 |
| Deposited By: | Narimah Nawil |
| Deposited On: | 01 Feb 2016 03:51 |
| Last Modified: | 12 Mar 2018 03:36 |
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