Tei, Y. Z. and Marsono, M. N. and Shaikh-Husin, N. and Hau, Y. W. (2013) Network partitioning and GA heuristic crossover for NOC application mapping. In: Proceedings - IEEE International Symposium on Circuits and Systems.
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Official URL: http://dx.doi.org/10.1109/ISCAS.2013.6572074
Abstract
Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic algorithm approach that incorporates network partitioning and heuristic crossover techniques to improve the NoC application mapping. Our experiment on VOPD (video object plane decoder) shows that our proposed method results in only 0.2% to 0.8% communication cost difference compared to global optimal mapping and 6% better communication cost compared to technique using conventional GA.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Uncontrolled Keywords: | network partitioning, Network-on-chip, application mapping, genetic algorithm |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 51193 |
| Deposited By: | Haliza Zainal |
| Deposited On: | 27 Jan 2016 01:53 |
| Last Modified: | 15 Aug 2017 06:14 |
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