Modeling the effect of velocity saturation in nanoscale MOSFET

Abstract

MOSFET scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. The introduction of 65 nm and 90 nm process technology offer low power, high-density and highspeed generation of processor with latest technological advancement. When gate length is scaled into nanoscale regime, second order effects are becoming a dominant issue to be dealt with in transistor design. In short channel devices, velocity saturation has redefined the current-voltage (I-V) curve. New models have been modified and studied to provide a better representation of device performance by understanding the effect of quantum mechanical effect. This thesis studies the effect of velocity saturation on transistor’s internal characteristic and external factor. Velocity saturation dependence on temperature, substrate doping concentration and longitudinal electric field for n-MOSFET are investigated. An existing currentvoltage (I-V) compact model is utilized and modified by appending a simplified threshold voltage derivation and a more precise carrier mobility model. The compact model also includes a semi empirical source drain series resistance modeling. The model can simulate the performance of the device under the influence of velocity saturation. The results obtained can be used as a guideline for future nanoscale MOS development.