Ibrahim, Zuwairie and Zainal Abidin, Amar Faiz and Adam, Asrul and Khalil, Kamal and Ahmed Mukred, Jameel Abdulla and Abdul Salam, Mohammad Nazry and Shaikh-Husin, N. and Tan, Zhe Hong and Md. Yusof, Zulkifli (2011) A two step binary particle swarm optimization approach for routing in VLSI. In: Sixth International Conference On Innovative Computing, Information And Control (Icicic 2011).
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Official URL: http://dx.doi.org/10.1109/CIMSim.2011.21
Abstract
Manipulation of wire sizing, buffer sizing, and buffer insertion are a few techniques that can be used to improve time delay in very large scale integration (VLSI) circuit routing. This paper enhances an existing approach, which is based on Particle Swarm Optimization (PSO) for solving routing problem in VLSI circuits. A two-step Binary Particle Swarm Optimization (BPSO) approach, which is based on BPSO, is chosen in this study to improve time delay through finding the best path of wire placement with buffer insertion from source to sink. The best path of wire placement is found in the first step by the first BPSO and then the second BPSO finds the best location of buffer insertion along the wire. A case study is taken to measure the performance of the proposed model and the result is obtained compared with the previous PSO approach for VLSI routing. © 2012 ICIC International.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Uncontrolled Keywords: | Wires, Routing, Delay effects, Very large scale integration, Particle swarm optimization, Computational modeling, Delay, binary particle swarm optimization, very large scale integrated circuit, routing problem, buffer insertion, interconnect |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 45528 |
| Deposited By: | Haliza Zainal |
| Deposited On: | 10 Jun 2015 03:01 |
| Last Modified: | 30 Aug 2017 07:44 |
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