A binary particle swarm optimization approach for buffer insertion in VLSI routing

Abstract

Time delay in very large scale integration circuit routing can be improved using several techniques such as intelligent selection of the size of wire and buffer, and strategic buffer placement.This paper proposes the use of Binary Particle Swarm Optimization to find the best selection of the size of wire and buffer, and ideal location of buffer insertion along the wire. For the proposed approach, a particle epresents a possible solution of the buffer placement problem. The time delay produced by the proposed solution of each particle is then calculated. The particle will try to improve its solution by trying to replicate its best record and swarm best record. The process is repeated until stopping condition is achieved. Swarm best record is taken as the best solution obtained by the proposed approach. A case study is taken to measure the performance of the proposed approach. The proposed approach has a good potential in VLSI routing and can be extended in future.