High-performance digital filter in FPGA

Abstract

Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application- specific integrated circuits (ASICs) for higher rates. Based on the study digital filter which is Infinite Impulse Response (IIR) filter, the filter is generally used in the lower sample rates, that is less than 200 kHz (2009) [2]. These filters are used over a wide range of sample rates and are well supported in terms of tools, software, and IP cores. In this research, a high performance and area optimized infinite impulse response (IIR) filter realization in field programmable gate arrays (FPGAs) is proposed. The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. The main goal of this project is to mapping data flow graphs (DFGs) from the BiQuad architecture direct form II of Infinite Impulse Response filtering algorithms into application specific structure is considered. This filter realizes BiQuad Methods was structured with the high throughput, high clock frequency (Fmax), low Critical Path Delay (CPD), and low Latency (L). Optimization method is proposed which provides designing pipelined structures, concurrent, minimal resource utilization and minimized sensitivity to truncation errors. A digital filter which is compatible with simulation tool (software) Verilog HDL Quartus II and Matlab presented in preliminary results chapter 5.