Second-stage tuning procedure for analogue CMOS design reuse methodology

Abstract

Proposed is a two-stage analogue circuit design reuse methodology by extending existing fabrication process rescaling procedures with a follow-on systematic tuning procedure stage based on DC output voltage scaling. It increases the potential for design reuse with short-channel MOSFET circuit designs when compared to the current single-stage rescaling work. Two Miller amplifier circuits were designed in 0.18 and 0.13µm CMOS processes in order to analyse circuit performance achieved with the proposed method compared to the existing methods. The additional tuning stage results in an improved amplifier gain up to 16dB and up to 2.5 times faster settling time compared to single-stage scaling with 33 power reduction and 28 smaller silicon area when compared to the original design.