Systolic array architecture and its application in finite impulse response filter design

Abstract

This project presents the methodology involved in mapping a computing algorithm onto Systolic Array (SA) architecture and its implementation in designing a high computational throughput Finite Impulse Response (FIR) filter. As in many applications of Digital Signal Processing (DSP), FIR filtering requires enormous computing power, especially for applications in real-time environment where fast computations of data is demanded. Fortunately, the FIR filter algorithm is a compute-bound computation, and speeding up this computation can be achieved through systolic approach. Prior to designing the SA FIR filter hardware module in Quartus II, the FIR filter was first designed and analyzed via MATLAB to obtain the filter coefficients and simulation results needed in hardware design. Verification and performance analyses of the SA FIR filter were done based on both simulation results from MATLAB and hardware designs. Simulation result of the SA FIR filter proved the capability of SA architecture to produce high computational throughput, but at the expense of a large number of resources. In addition, the simulation results displayed some limitations of this particular design in terms of its response time and accuracy of the results. Thus, improvements of the design have been proposed to increase its performance.