Universiti Teknologi Malaysia Institutional Repository

VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm

Rajah, Avinash (2005) VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.


Official URL: https://core.ac.uk/display/11779366


As artificial neural networks continue to gain popularity in the domain of pattern recognition, there have been growing demands for these models to be executed at high-speeds. Thus, to cater to this need, the VLSI design and implementation of a neurohardware for high-speed pattern recognition is proposed in this research. The UTM-Neuroprocessor implements the Kohonen Neural Network for pattern classification. High-speed pattern classification by the neural paradigm is achieved through massively parallel execution based on the neuron-parallel processing approach. For proof of concept purposes, a 10x10 UTM-Neuroprocessor, which implements a 10x10 Kohonen network, was developed in this work. The design and rapid FPGA prototyping of the neuroprocessor was achieved using VHDL and the Altera Nios embedded system development kit. The FPGA-based prototype of the 10x10 UTM-Neuroprocessor is able to function at a frequency of 100 MHz and delivers performances up to 5.079 GCPS and 2.285 GCUPS. Software components, including a VB-based GUI, were also developed to allow execution of pattern recognition applications on the UTM-Neuroprocessor. For efficient VLSI implementation of the UTM-Neuroprocessor, the combined FPGA-VLSI approach was proposed. Correspondingly, the VLSI design of a 2x2 array computation engine, termed the Array_2x2 microchip, was developed in the AMI 0.5µm process technology and fabricated at the Europractice IC foundry. The fabricated Array_2x2 microchip can be applied to produce a 2x2 UTM-Neuroprocessor, in the combined FPGA-VLSI implementation approach. The design consumes an area of 16.9 mm2 on silicon and is encapsulated in 84-pin PGA package. SPICE simulations of the Array_2x2 design proved functionality at an operating frequency of 90 MHz. The microchip is able to deliver performances of up to 169.41 MCPS and 75.78 MCUPS MCUPS for a 2x2 UTM-Neuroprocessor

Item Type:Thesis (Masters)
Additional Information:Thesis (Master of Engineering (Electrical)) - Universiti Teknologi Malaysia, 2005; Supervisor : Prof. Dr. Mohamed Khalil Mohd. Hani
Uncontrolled Keywords:microchip, silicon
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:2946
Deposited By: Dina Amalia Nordin
Deposited On:25 May 2007 08:45
Last Modified:25 Jun 2018 00:42

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