SoC test scheduling algorithm using enhanced rectangle packing

Abstract

The System-on-Chip (SoC) test scheduling algorithm based on rectangle packing was previously proposed by Iyengar et al. in 2002. This method had been proven its effectiveness on SoC test application time optimization. Xia et al. further improve the flexibility of rectangle packing approach by implementing the distributed rectangle binpacking approach which allows core wrapper pins from one particular core to be assigned to non-consecutive SoC Test Access mechanism (TAM) through vertical partitioning of core rectangles. However, the above mentioned methods still result in significant idling time. Therefore, this project proposes a new scheduling method, namely the enhanced rectangle packing, which is an extension to the original rectangle packing and distributed rectangle packing. The proposed algorithm horizontally partitioned the core rectangles to obtain rectangles of smaller size for idling time reduction, which in turn successfully shorten the total test application time for a SoC. Experimental results conducted on ITC’02 SoC test benchmark circuits show the effectiveness of the enhanced rectangle packing algorithm in reducing SoC test application time for up to 6% in maximum.