Khalil-Hani, Mohamed and Ahmad, llliasaak and Hau, Yuan (2007) Electronic system level (ESL) design methodology for IP-based system-on-chip (SoC). In: International Conference on Robotic, Vision, Information and Signal Processing (ROVISP 2007), 2007, Park Royal, Penang.
Full text not available from this repository.
Abstract
Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Uncontrolled Keywords: | Electronic system level, system-on-chip |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 13949 |
| Deposited By: | Liza Porijo |
| Deposited On: | 16 Aug 2011 09:56 |
| Last Modified: | 06 Aug 2017 01:40 |
Repository Staff Only: item control page
