SystemC-based HW/SW co-simulation platform for system-on-chip (SoC) design space exploration

Abstract

The development of digital designs today is much more complex than before, as they now impose more severe demands and require greater number of functionalities to be conceived. The current approach, based on the Register Transfer Level (RTL) design methods, can result in extremely long simulation time compounded with time-consuming verification process. Hence, today digital system design begins with modeling at a higher level of design abstraction, that is, the Electronic System Level (ESL). This paper presents a hardware-software (HW/SW) co-simulation environment based on SystemC for application in the design of system-on-chip (SoC). We discuss the SystemC modeling of the hardware and the software parts of the system, and the inter-process communication module of the co-simulation platform. Its objective is to help designers obtain an appropriate HW/SW partitioning that satisfy specified area-speed design tradeoffs. Besides, an early system verification can also carried out with high simulation speed. A case study of a SoC implementing Elliptic Curve Cryptography (ECC) is presented to validate the co-simulation platform in terms of system functionality, verification and design space exploration.