Saad, Ismail and Lee, Razak M. A. and Munawar, A. R. and Ahmadi, M. Taghi and Ismail, Razali (2009) Numerical analysis of vertical double gate mosfets (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor. In: Nanoscience And Nanotechnology. AIP Conference Proceedings, 1136 . American Institute of Physics, USA, 840 -844. ISBN 978-0-7354-0673-5
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Official URL: http://dx.doi.org/10.1063/1.3160269
Abstract
Numerical analysis of vertical double-gate MOSFETs (VDGM) that incorporates dielectric-pocket (DP) is addressed in this paper for the suppression of short-channel effects (SCE) and bulk punch-through. The comparison between standard and VDGM-DP revealed the advantages of DP for inhibition of SCE. The transfer and output characteristics of the VDGM-DP indicates a reasonable value of threshold voltage (V(T)), drive and off -leakage current (ION and I(OFF)), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The DP incorporated on top of transistor turret is revealed to increase the saturation current I(Dsat) due to drain-end electric field reduction that improved the carrier mobility and the drain current tremendously.
| Item Type: | Book Section |
|---|---|
| Uncontrolled Keywords: | vertical MOSFET, DIBL, double gate, dielectric-pocket |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 13017 |
| Deposited By: | Liza Porijo |
| Deposited On: | 13 Jul 2011 02:14 |
| Last Modified: | 13 Jul 2011 02:14 |
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