Modeling of a ladder logic processor for high performance programmable logic controller

Abstract

Today, programmable logic controllers (PLCs) is the dominant technology deployed in control automation systems in modern factories. The main modeling method of the PLC is based on ladder logic diagrams (LLDs). However, as a system gets more complex, LLD implementations poses a stumbling block in the design of more complex and real-time PLCs. Consequently, in this paper, a novel architecture for a high performance LLD implementation, which we call the Ladder Logic Processor, is proposed. In the proposed architecture, each computation of the underlying ladder logic is performed at a fixed number of clock cycles per ladder rung, regardless of the number of steps involved. Notwithstanding, the technique maintains the existing LLD paradigm where every rung is processed sequentially. The LLDs are targeted for implementation in Field Programmable Gate Arrays (FPGAs). Experimental work performed to evaluate the performance of the proposed architecture shows promising results.