Universiti Teknologi Malaysia Institutional Repository

Implementation of reconfigurable viterbi decoders in hardware

Noor Batcha, Mohamed Farid (2010) Implementation of reconfigurable viterbi decoders in hardware. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.



Channel coders are widely used in digital transmissions where data can be corrupted due to interference. They are used in a large proportion of digital transmission and digital recording systems, including digital mobile telephony and digital television broadcast, compact disc, and magnetic disk reading. Viterbi decoder is one of the most widely used channel decoders that are used for decoding data that are encoded using convolutional forward error correction codes. This research investigates an adaptive channel coder that is able to switch between few configurations depending on the channel conditions. Channel codes consist of encoders and decoders, and since encoders are rather simple, the main focus of the research is towards the decoders. The research explores into an optimized shared hardware structure between various Viterbi decoders especially of those being used in current technologies such as General Packet Radio Service (GPRS), Enhanced Data rates for GSM Evolution (EDGE), and Worldwide Interoperability for Microwave Access (Wimax). The research looks into optimized methods of memory management and is also aimed for high throughput to be used for high speed applications that are a trend for new and upcoming technologies. Initially the performance of various configuration of Viterbi decoder with respect to different channel conditions was looked into to select few suitable Viterbi decoders to be implemented on Field Programmable Gate Array (FPGA). The final implementation on FPGA combines three Viterbi decoders into a single core. The gain in area of the three Viterbi existing separately when compared to the joint hardware is about 15 %, with no loss in processing speed and throughput. The latency is measured to be a minimum amount with respect to the data size. For a packet size of 100 information bits and code rate r=1/2 the latency would be 162 cycles. The main idea in having a shared hardware structure was to basically map the trellis structure of the smaller Viterbi configuration over the larger one, thereby not taking any extra hardware of its own. The significance would be a reduced complexity of various Viterbi decoders existing on a single shared hardware.

Item Type:Thesis (Masters)
Additional Information:Thesis (Sarjana Kejuruteraan (Elektrik)) - Universiti Teknologi Malaysia, 2010; Supervisor : Assoc. Prof. Dr. Ahmad Zuri Sha'ameri
Uncontrolled Keywords:decoders (electronics), channel coders
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:12722
Deposited On:27 Jun 2011 12:56
Last Modified:13 Sep 2017 12:28

Repository Staff Only: item control page