Universiti Teknologi Malaysia Institutional Repository

A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree

Rahim At Samsuddin, H. A. and Ab. Rahman, A. A. H. and Andaljayalakshmi, G. and Ahmad, R. B. (2008) A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree. In: Proceedings of the International Conference on Computer and Communication Engineering 2008, May 13-15, 2008, Kuala Lumpur, Malaysia.

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Abstract

This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three different types of genetic algorithms: simple genetic algorithm (SGA), steady-state algorithm (SSGA) and adaptive genetic algorithm (AGA) are employed in order to examine their performances in converging to their global minimums. Experimental results on Microelectronics Center of North Carolina (MCNC) benchmark problems show that the developed algorithm achieves an acceptable performance quality to the slicing floorplan. Furthermore, the robustness of genetic algorithm also has been investigated in order to validate the performance stability in achieving the optimal solution for every runtime. This algorithm demonstrates that SSGA converges to the optimal result faster than SGA and AGA. Besides that, SSGA also outperforms SGA and AGA in terms of robustness

Item Type:Conference or Workshop Item (Paper)
Uncontrolled Keywords:genetic algorithms, binary tree
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:9961
Deposited By: Siti Najwa Hanim Kamarulzaman
Deposited On:30 Jun 2010 01:42
Last Modified:17 May 2013 01:12

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