High-level design and synthesis of VLSI cell placement algorithm

Abstract

Nowadays, chip manufacturers are concerned with the fast time-to-market of the integrated circuit (IC), therefore fast time cycle from design to manufacturing is essential to achieve this goal. The physical design of Very Large-Scale Integration (VLSI) placement is the process of determining the position of each cell on a die surface such that there are no cell overlaps with each other. Moreover, this process is also identifying which affects the timing, routability, power consumption, and performance of a chip. In VLSI cell placement, the most time-consuming task is the IC physical design flow as it involves finding the optimum placement of millions of standard cells and macros in a chip floorplan. The purpose of this study is to improve modern VLSI placement algorithms by using Hardware (HW)/ Software (SW) codesign and High-Level Synthesis (HLS) methodology. The methods in chip floorplan placements can be generally divided into three categories: partition-based placement methods, simulated annealing based methods, and analytical approaches. In this research, the placement algorithm is based on the simulated annealing, and C/C++ programming is developed and validated using standard academic benchmarks from the International Symposium on Physical Design (ISPD) design competition. Some of the critical functions such as the wirelength calculation are synthesized from C to Register-Transfer Level (RTL) using Vivado HLS software for a custom HW implementation and the rest of the algorithm such as data parsing and memory accesses will remain in C, and co-simulated with the custom hardware block. Therefore, this project offers the possibility of using HLS design for VLSI cell placement process where it is proven that using RTL design has improved the execution time in certain functions such as wirelength calculation. Moreover, HLS offers more options in terms of design space exploration as compared to traditional RTL methodology.