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Temperature variation operation of mixed-VT 3T GC-eDRAM for low power applications in 2Kbit memory array

Abdo, Hussien and Alias, N. Ezaila and Hamzah, Afiq and Kamisian, Izam and Tan, M. L. Peng and Sheikh, U. Ullah (2022) Temperature variation operation of mixed-VT 3T GC-eDRAM for low power applications in 2Kbit memory array. International Journal of Integrated Engineering, 14 (3). pp. 193-201. ISSN 2229-838X

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Official URL: http://dx.doi.org/10.30880/ijie.2022.14.03.021

Abstract

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-VT 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400 MHz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs (others' work in K. Sharma et al.and A. Goyal et al.) the retention power of the proposed GC-eDRAM is around 80-90% lower.

Item Type:Article
Uncontrolled Keywords:Drt, Embedded memories, Gc-dram, Leakage
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:Electrical Engineering
ID Code:99444
Deposited By: Widya Wahid
Deposited On:27 Feb 2023 04:50
Last Modified:27 Feb 2023 04:50

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