Ooi, Chia Yee and Fujiwara, Hideo (2006) A new class of sequential circuits with acyclic test generation complexity. In: 24th IEEE International Conference on Computer Design (ICCD'06), 1-4 Oct. 2007 .
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Official URL: http://dx.doi.org/10.1109/ICCD.2006.4380851
This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation procedure for acyclically testable sequential circuits and elaborate a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuit. Since the class of acyclically testable sequential circuits is larger than the class of acyclic sequential circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.
|Item Type:||Conference or Workshop Item (Paper)|
|Uncontrolled Keywords:||acyclic test generation, design-for-test, sequential circuits, test generation complexity|
|Deposited By:||Nurunnadiah Baharum|
|Deposited On:||27 Jul 2009 03:14|
|Last Modified:||27 Jul 2009 03:14|
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