Compact device modelling of interface trap charges with quantum capacitance in mos2-based field-effect transistors

Abstract

An effective way to obtain interface trap density in transition metal dichalcogenide field-effect transistors (FETs) via compact device modelling is presented in this study. A computationally efficient model is utilised to evaluate the interface trap charges in a MoS2-based FET device. This model improves the accuracy of the computed surface potential, which is affected by trap charges. The existence of trap states on the interface level can be confirmed by studying the capacitance versus gate voltage (C-Vg) relationship. Most of the previously proposed models ignore the effect of the quantum capacitance when predicting the electrical performance of MoS2-FETs. The electrical performance of a metal-oxide-semiconductor FET with a two-dimensional (2D) molybdenum disulphide (MoS2) channel that introduces a quantum capacitance C q by including a gate is evaluated. The gate quantum capacitance C q in parallel with the interface trap capacitance C it is a second capacitance in series with the gate oxide capacitance C ox and MoS2 capacitance C M o S2. This research explores the process of evaluating the interface trap density D from published C-V g experimental data of MoS2-based FETs. Using the evaluated trap density values, the device parameters are calculated by considering the relative permittivity of the dielectric hafnium oxide (HfO2) layer, surface potential, interface trap charge Q and interface trap capacitance C. Finally, the calculated and experimental data are compared through the normalised root-mean-square deviations (RMSD) to validate the accuracy of the model.