Ooi, Chia Yee and Clouqueur, Thomas and Fujiwara, Hideo (2007) Analysis of test generation complexity for stuck-at and path delay faults based on tk-notation. IEICE Transaction on Information and System, Vol E90-D . pp. 1202-1212. ISSN 0916-8532, 1745-1361 (online)
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Official URL: http://www.ieice.org/eng/trans_online/
Abstract
In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced Ï„k-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | easily testable, stuck-at faults, path delay faults, test generation complexity |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Electrical Engineering |
| ID Code: | 8610 |
| Deposited By: | INVALID USER |
| Deposited On: | 06 May 2009 04:40 |
| Last Modified: | 06 May 2009 04:53 |
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