Performance evaluation of 14 nm FinFET-Based 6T static random access memory cell functionality for DC and transient analysis

Abstract

This research focuses on the evaluation of the characteristics of the independently controlled FinFET gate structure in a static random access memory (SRAM) circuitry. It is developed based on the BSIM-CMG model for common gate FinFET. The independently controlled FinFET gate was constructed using two parallel connections of the common FinFET gate, however without the gate terminal, thus allowing it to be controlled independently. SRAM 6T scheme was chosen benchmarked with the conventional common FinFET SRAM gate. Netlists for NMOS and PMOS devices and SRAM circuitry are constructed and simulated with a HSPICE tool. The IV characteristic of this proposed structure has better drive currents with 1.1 times for NMOS and 1.3 times for PMOS compared to the conventional common FinFET gate, as a result of the capacity for the dynamic gate to adjust voltage. There is a significant reduction in the leakage current in this proposed structure compared to the conventional common FinFET gate, the reduction leakage for NMOS and PMOS is up to 3 times the order magnitude. The results of the SRAM circuitry constructed by this proposed independently controlled the FinFET gate structure has shown that the read and write margin are higher than the conventional common FinFET SRAM gate design. The proposed structure in SRAM design is beneficial for low power application designs as it has a lower standby current. Furthermore, different back-gate bias schemes for this structure are explored. The optimum back-gate scheme is proposed where there is reversed biased on pull down device and pull up device, with the dynamic gate voltage control on the pass gate device.