Interconnection and damping assignment passivity-based controller for multilevel inverter

Abstract

This thesis proposes an Interconnection and Damping Assignment Passivity- Based Controller (IDA-PBC) to control a 5-level Cascaded H-Bridge Multilevel Inverter (CHMI). The proposed IDA-PBC uses the Port-Controlled Hamiltonian (PCH) theory to modify the CHMI system energy by adding damping, thereby modifying dissipation structures related to dynamics and stability. The objective is to maintain output voltage regulation, resulting in fast response and low Total Harmonic Distortion (THD) values. Although the proposed IDA-PBC control algorithm showed outstanding performance during transient and nonlinear load condition, further improvements are required during no-load condition. To address this, improvements in the form of modification to the proposed IDA-PBC algorithm was made by adding a single loop Proportional-Integral (PI) controller at the voltage side, which was aimed at regulating the voltage before it was fed back into the IDAPBC. In order to verify the viability of the proposed IDA-PBC-PI controller for the CHMI, a simulation study was conducted using MATLAB/Simulink at a 20 kHz switching frequency and 1 µs sample time. The controller was tested at five load conditions, namely, steady state, no-load to full-load, load uncertainty, structural uncertainty and nonlinear load condition. The performance of the proposed controller showed regulated output voltage while maintaining THD values below 5% in all load conditions and a maximum of 220 µs response time during load uncertainty. The simulation results revealed the superiority of the proposed controller compared to the conventional double loop PI controller and the conventional IDA-PBC in terms of transient response, THD value, as well as regulation of the output voltage. The feasibility of the proposed IDA-PBC-PI controller was validated by developing its proof-of-concept hardware prototype. The simulation and experimental results obtained based on a 3 kHz switching frequency and 38 µs sample time were found to be consistent, which confirmed the capability of the proposed controller in controlling the 5-level CHMI output voltage.