Razak, F. N. A. and Talip, M. S. A. and Yakub, M. F. M. and Khairudin, A. S. M. and Izam, T. F. T. M. N. and Zaman, F. H. K.
(2017)
*High Speed Numerical Integration Algorithm Using FPGA.*
Journal of Fundamental and Applied Sciences, 9
(4).
pp. 131-144.
ISSN 1112-9867

Full text not available from this repository.

Official URL: http://dx.doi.org/10.4314/jfas.v9i4S.7

## Abstract

Conventionally, numerical integration algorithm is executed in software and time consuming to accomplish. Field Programmable Gate Arrays (FPGAs) can be used as a much faster, very efficient and reliable alternative to implement the numerical integration algorithm. This paper proposed a hardware implementation of four numerical integration algorithms using FPGA. The computation is based on Left Riemann Sum (LRS), Right Riemann Sum (RRS), Middle Riemann Sum (MRS) and Trapezoidal Sum (TS) algorithms. The system performance is evaluated based on target chip Altera Cyclone IV FPGA in the metrics of resources utilization, clock latency, execution time, power consumption and computational error compared to the other algorithms. The result also shows execution time of the FPGA are much faster compared to the software implementation.

Item Type: | Article |
---|---|

Uncontrolled Keywords: | numerical integration algorithm, FPGA, Riemann sum |

Subjects: | Q Science > QA Mathematics |

Divisions: | Science |

ID Code: | 81129 |

Deposited By: | Narimah Nawil |

Deposited On: | 24 Jul 2019 03:34 |

Last Modified: | 24 Jul 2019 03:34 |

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