Universiti Teknologi Malaysia Institutional Repository

Characterization of 50 nm MOSFET with dielectric pocket

Fauzan, Zul Atfyi and Saad, Ismail and Ismail, Razali (2007) Characterization of 50 nm MOSFET with dielectric pocket. Jurnal Fizik Malaysia, 28 (3-4). pp. 93-98. ISSN 0128-0333

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Abstract

Characterizat ion of a metal-oxide-semi conductor field effect tran sistor incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE ) is demonstrated by using 2D numerical simulation. An analysis of 120 nm and 50 nm channel length (LJ wit h DP incorp orated between the chann el and source/drain has been done successfu lly. The DP has suppressed short channel effect (SCE) witho ut the need s of increasi ng the channel dopin g pro file. With uniform dopi ng of 10" em' and 10' 0 ern' for channel and source/drain region respectively, a reduc tion of 2.5 decade s of leakage current (lOFF) was obtained in MOSFET with DP without altering the drive current (ION) for 120 nm channe l length . A very low leakage current of 0.002 pAl l'm is obtained for DP device with drain voltag e (Vos) of 0.1 V and increase to 18 pAll'm with Vns = l.OV for 120 nm Lg. Th is obtained with drive current of 0.5 rnA and 5 rnA respectively. Meanwhile, with L. = 50 nm, 700 nAll'm leakage current and 1 mAll'm drive current was o bserved. With the same doping profile s, a reduct ion of 1.4 decades of 10 FF was shown by the incorpora tion of DP for Lg = 50 nm. Thus, the incorporation of DP will enhance the electri cal perform ance and give a very good control of the SCE for sca ling the MOSFET in nanometer regime for future developme nt of nanoe lectronics product.

Item Type:Article
Uncontrolled Keywords:MOSFET, dielectric pocket, electrical
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QC Physics
Divisions:Electrical Engineering
ID Code:8046
Deposited By: Norshiela Buyamin
Deposited On:25 Mar 2009 03:36
Last Modified:25 Mar 2014 07:02

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